The present invention relates to digital-to-analog converter circuits.
Conventionally, as one of digital-to-analog converter circuits, there is a current output type digital-to-analog converter that is ideally suited for image signal processing. FIG. 11 is a circuit diagram depicting one example of a current output type digital-to-analog converter circuit formed on a semiconductor chip, where its input digital data is 4 bits.
In FIG. 11, the current output type digital-to-analog converter circuit 50 has sixteen current source cells 51a-51p disposed at regular intervals. Each of the current source cells 51a-51p comprises first and second constant current sources G1 and G2, respectively, that share an output terminal 52 thereof.
Each of the output terminals 52 is electrically connected to first and second analog output lines 54a and 54b via a changeover switch SW, respectively. Each of the changeover switches SW is electrically connected to a decoder circuit, which is not shown. Each changeover switch SW is designed so that the output terminal 52 is electrically connected to either of a first analog output line 54a or a second analog output line 54b in accordance with a control signal from the decoder circuit.
The first constant current source G1 of the respective current source cells 51a-51p is connected to a first power supply pad P1 via a first power supply line L1, respectively. The second constant current source G2 of the respective current source cells 51a-51p is also connected to a second power supply pad P2 via a second power supply line L2, respectively. The first and second power supply lines L1 and L2 are arranged along the respective current source cells 51a-51p in parallel to each other.
On the left-most end of the first power supply line L1 in FIG. 11 is formed the first power supply pad P1, to which direct-current (DC) voltage Vdd is applied to supply DC voltage to the first constant current source G1 of the respective current source cells 51a-51p. On the right-most end of the second power supply line L2 in FIG. 11 is formed the second power supply pad P2, to which DC voltage Vdd is also applied to supply DC voltage to the second constant current source G2 of the respective current source cells 51a-51p. 
The changeover switch SW selected in accordance with the input digital data to the decoder circuit is turned ON or OFF. The currents generated at the first and second constant current sources G1 and G2 of the current source cells 51a-51p are summed, and the resulting summed output current is output as an analog signal from either of output terminals PO1 or PO2. That is, digital-to-analog conversion is performed.
The value of the current output from each of the current source cells 51a-51p is required to be identical. For the output currents from the current source cells 51a-51p to be identical, the voltages supplied to the current source cells 51a-51p all need to be identical. Thus, the digital-to-analog converter circuit 50 shown in FIG. 11 is designed to supply DC voltage Vdd, in different directions, to the first and second constant current sources G1 and G2 of the current source cells 51a-51p via the first and second power supply lines L1 and L2, respectively.
More specifically, line resistances R1a-R1p exist across the first power supply line L1, and line resistances R2a-R2p exist across the second power supply line L2. It should be appreciated that the line resistances R1a-R1p and R2a-R2p all have the same value. Thus, the first constant current source G1 of the current source cells 51a-51p has an increasingly lower voltage supplied thereto, because the further it is away from the first power supply pad P1, the greater the amount of voltage drop. The second constant current source G2 of the current source cells 51a-51p has an increasingly lower voltage supplied thereto, because the further it is away from the second power supply pad P2, the greater the amount of voltage drop.
Meanwhile, each of the constant current sources G1 and G2 of the current source cells 51a-51p is all driven by a common voltage. Thus, the value of the output current output by the current source cells 51a-51p is dependent upon a potential difference between the bias supply terminals (not shown) of the constant current sources G1 and G2 and the power supply terminals of the constant current sources G1 and G2 connected to the first and second power supply lines.
As a result, at each of the current source cells 51a-51p, the voltages supplied to the first and second constant current sources G1 and G2 and the cell positions are in reverse direction to each other. Accordingly, the output currents of the first and second constant current sources G1 and G2 at the respective current cells 51a-51p also similarly have reverse current output characteristics depending upon the cell position. It should be appreciated that because the output current at the respective current cell 51a-51p is the sum of the currents output from the two constant current sources G1 and G2 within that current cell, the output current from the current cell 51a-51p remains constant as the effects of the power supply lines L1 and L2 cancel each other out.
A method to correct the voltage drops due to the line resistances R1a-R1p and R2a-R2p of the power supply lines L1 and L2 to make the values of the output currents output from the current source cells 51a-51p identical, is a current output type digital-to-analog converter circuit shown in FIG. 12. The current output type digital-to-analog converter circuit 60 shown in FIG. 12 omits the second power supply pad P2, so that DC voltage is supplied directly from the first power supply pad P1 to the first and second power supply lines L1 and L2. In this case, the first power supply pad P1 is electrically connected to the right-most end of the second power supply line L2 via a bypass line L3. It should be appreciated that the bypass line L3 has a line resistance R3 in a similar manner to the first and second power supply lines L1 and L2. Thus, to the second power supply line L2 is supplied the value of the DC voltage Vdd less the voltage drop due to the line resistance R3. In this case, the value of the output currents output from the respective current source cells 51a-51p are also similarly made identical.
However, as shown by the characteristic curve X1 in FIG. 13, the amount of voltage drop at each position of the first power supply line L1 due to the line resistances R1a-R1p actually changes as a quadratic function. Similarly, as shown by the characteristic curve X2 in FIG. 13, the amount of voltage drop at each position of the second power supply line L2 due to the line resistances R2a-R2p actually changes as a quadratic function.
More specifically, the current value at portions of the first and second power supply lines L1 and L2 that are closer to the first and second power supply pads P1 and P2 is greater, whereas the current equivalent to one cell of the current source cells 51a-51p flows at portions of the first and second power supply lines L1 and L2 that are furthest away therefrom. In this way, if the current flowing through the first and second power supply lines L1 and L2 increases, the amount of voltage drop developed across the first and second power supply lines L1 and L2 having the constant line resistance is an integral value of the voltage drops across the respective line resistances R1a-R1p and R2a-R2p. As a result, the characteristic curves X1 and X2 nearly follow the quadratic function.
Thus, at each of the current cells 51a-51p, the output current of the first constant current source G1 has a characteristic as represented by the characteristic curve X11 in FIG. 14, while the output current of the second constant current source G2 has a characteristic as represented by the characteristic curve X22 in FIG. 14. Here, the output current at the respective current cell 51a-51p is a sum of the currents output, respectively, from the two constant current sources G1 and G2 within that current cell. Thus, the output current of each current source cell 51a-51p has a characteristic as represented by the characteristic curve X3 shown in FIG. 15; as such, the values of the output currents of the current cells 51a-51p would not become identical, although the effects of the power supply lines L1 and L2 might be reduced.
The current output type digital-to-analog converter circuit shown in FIG. 12 also has a similar problem. The present invention is intended to solve the afore-described problem and has as its objective to provide a digital-to-analog converter circuit such that the values of the output currents output from the respective current source cells are identical regardless of the position of the current source cells relative to the power supply lines.
The invention according to claim 1 is a digital-to-analog converter circuit, wherein a plurality of current source cells having a first constant current source and a second constant current source are arranged in one direction; a first power supply line corresponding to the first constant current source of the respective current source cell and a second power supply line corresponding to the second constant current source of the respective current source cell are arranged in such a direction that the current source cells are arranged; a changeover switch disposed respectively for the respective current source cell is selectively operated in accordance with input digital data so that the output current from the current source cell is output to either of a first analog output line or a second analog output line, said digital-to-analog converter circuit is characterized by: line widths of said first and second power supply lines being modified depending upon the position at which they are formed, respectively, so that the average value of the voltages supplied to said respective current source cells becomes uniform.
The invention of claim 2 is the digital-to-analog converter circuit according to claim 1, wherein the first and second power supply lines are modified so that the line widths thereof become continuously narrower as they are further away from the power supply pads, respectively.
The invention of claim 3 is the digital-to-analog converter circuit according to claim 2, wherein the first and second power supply lines are in the form of a right triangle, respectively, and are disposed so that the hypotenuses thereof are opposite to each other.
The invention of claim 4 is the digital-to-analog converter circuit according to claim 1, wherein the first and second power supply lines are modified so that the line widths thereof become narrower in stepwise manner as they are further away from the power supply pads, respectively.
The invention of claim 5 is the digital-to-analog converter circuit according to claim 1, wherein the first and second power supply lines comprise a plurality of lines having a constant line width; and the lines are modified so that the number of the lines becomes smaller as they are further away from the power supply pads, respectively.
The invention of claim 6 is the digital-to-analog converter circuit according to claim 4, wherein the first and second power supply lines have one sides thereof modified in stepwise manner depending upon the position of the current source cell, and are disposed so that the one sides thereof are opposite to each other. According to the invention described in claims 1 through 6, by modifying the line widths of the first and second power supply lines to adjust the line resistance thereof, the average value of the voltage supplied to the respective current source cells is made uniform. Thus, the value of the output current output from the current source cells can be made identical regardless of the positions of the current source cells.
Additionally, according to the invention described in claims 2 and 4, the line resistances of the power supply lines can be adjusted easily. Still additionally, according to the invention described in claims 3 and 6, the area occupied by both of the power supply lines can be reduced, thereby enhancing the degree of integration for the digital-to-analog converter circuit.
Furthermore, according to the invention described in claim 5, the first and second power supply lines with the line widths thereof modified can be formed easily.